5.3 CMOS Logic Structures

以為例﹐說明下列各種logic structures。

CMOS Complementary Logic

Variations from the complementary CMOS gate include the following techniques :

Fig. 5-4 CMOS complementary gate.

Pseudo-nMOS Logic

The load device is a signal p-transistor, with the gate connected to VSS . Alternatively, the p-load may be connected as a constant-current source to provide better process tracking and optimized pull-down sizes. the main problem with the gate is the static power dissipation that occurs whenever the pull-down chain is turned on.

Fig. 5-5 Pseudo-nMOS Logic gate.

Dynamic CMOS Logic

It consists of an n-transistor logic structure whose output node is precharged to VDD by a p-transistor and conditionally discharged by an n-transistor connected to VSS . clk is a single-phase clock. The precharge phase occurs when clk=0. The input capacitance of this gate is the same as the pseudo-nMOS gate. The pull-up time is improved by virtue of the active switch, but the pull-down time is increased due to the ground switch.

Fig. 5-6 Basic CMOS dynamic gate.

Clocked CMOS Logic (C2MOS)

This from of gate was originally used to build low-power-dissipation CMOS logic. The reasons for the reduced dynamic power dissipation stem mainly from metal gate CMOS layout considerations and are not particular relevant in today's technologies. The main use of such logic structures at this time is to from clocked structures that incorporate latches or that interface with other dynamic from of logic. The gates have the same input capacitance as regular complementary gates but larger rise and fall times due to the series clocking transistors.

Fig. 5-7 A clocked CMOS gate.

Pass-Transistor Logic

Desgn of pass-transistor networks using Karnaugh map invlves constructing the cells in Karnaugh map in the normal manner. For instance, in the case of a 2-input XNOR gate.

Two-input XNOR gate implemented in pass-transistor logic：

(a)complementary;(b)single-polarity;(c)cross-coupled


CMOS Domino Logic

A modification of the clocked CMOS logic allows a single clock to precharge and evaluate a cascaded set of dynamic logic blocks. This involves incorporating a static CMOS inverter into each logic gate.

Fig. 5-8 CMOS domino logic gate.

Cascade Voltage Switch Logic ( CVSL )

It is differential style of logic requiring both true and complement signals to be routed to gates. Two complementary nMOS switch structures are constructed and then connected to a pair of cross-coupled p pull-up transistor.

Fig. 5-9 Cascade voltage switch logic gate.